(1) Field of the Invention
The present invention relates to solid-state imaging devices for detecting physical quantity distribution of visible light, electromagnetic waves, and particle radiation such as alpha rays and beta rays, and more particularly to a solid-state imaging device having an asynchronous counter which realizes a CDS operation of AD conversion circuit which receives output signals from the photoelectric conversion device arranged in rows and columns, the driving method thereof, and a camera.
(2) Description of the Related Art
In recent years, MOS image sensors (hereinafter referred to as “MOS sensors”) in which peripheral circuits such as an AD conversion circuit can be incorporated have been actively developed, and the number of products has been increasing, as a counterpart of Charge Coupled Devices image sensors (hereinafter referred to as “CCD sensor”), which have established their use as image sensors, that is, the key device in a digital camera and a video camera.
Unlike the CCD sensor using a specific semiconductor process, one of the features of the MOS sensor is its convenience. More specifically, a timing control circuit, a signal processing circuit and other circuits can be mounted on a single semiconductor chip.
The value of image sensor is determined by its image quality, and CCD sensors have established better quality in that regard. However, in recent years, a technology for performing CDS and analog-digital (analog/digital, A/D, AD) conversion essential after a signal is outputted from the pixel on the same chip as the MOS sensor has been developed, and MOS image sensors that are comparable with CCD sensors in image quality have been developed.
Here, a brief description is made for CDS which is signal processing specific to the image sensors. The signal levels read out from the pixels have a variation caused by offset. However, since the offset value can be read out immediately after the pixels are reset (this signal levels are referred to as reset levels), it is possible to obtain true pixel signal level by reading out the reset level and the signal level from the pixel, and subtracting the reset level from the signal level. This process is referred to as Correlated Double Sampling (CDS). Performing CDS on an analog signal is referred to as analog CDS, and performing CDS on a digital signal is referred to as digital CDS.
The following describes a conventional analog CDS. Various methods have been proposed for the analog CDS, in most of the methods, CDS is performed by subtracting the reset level from the signal level using a capacitor.
This method accompanies sampling on the capacitor, and thermal noise NThermal is sampled when closing a switch, which causes a problem that noise that cannot be fully removed by CDS is left. The following expression shows the thermal noise.Nthermal=kT/C (k: Boltzmann coefficient, T: absolute temperature, C: capacitance of capacitor)
To put it differently, although the thermal noise can be reduced by increasing the capacitance, the capacitance cannot be easily increased since there is a tradeoff between the area (resource on the chip) and the capacitance. Introducing a device having a larger capacitance per unit area can surely reduce the area. However, it does not change the inverse relationship described above. Furthermore, it should be noted that the C-V characteristic (voltage dependency of the capacitance) of the device used for the capacitor limits the performance.
On the other hand, when performing the digital CDS, it is not necessary to provide a capacitor that causes a problem with regard to area in the analog CDS.
Instead, digital CDS can be realized by performing an AD conversion for both a signal level and a reset level at high accuracy, and subtracting the values as digital values.
Conventionally, the analog CDS has been in the mainstream since in the digital CDS, low AD conversion accuracy leads to low CDS. On the other hand, advancement in AD conversion technology on MOS sensors improves the accuracy of digital CDS. Thus, along with improving accuracy of the AD conversion, efficient digital CDS has been requested.
Digital CDS can be realized in many ways, and Patent References 1: U.S. Pat. No. 5,877,715 and Patent Reference 2: Japanese Unexamined Patent Application Publication No. 2005-323331 disclose a digital CDS method in which asynchronous up/down counters are provided in each column of the column AD conversion circuits in the MOS sensor, AD conversion is performed by down-counting when reading the reset level, and another AD conversion is performed by up-counting when reading the signal level, and performs the following calculation on the counter has been proposed.(Signal level)−(Reset level)=(True signal level)
Note that, it is assumed that an asynchronous counter is suitable for a counter as a component in the column AD conversion circuit for accelerating and for improving the accuracy since the asynchronous counter is easy to adjust increasing frequency. Both the Patent Reference 1 and 2 utilize the asynchronous counters.
FIG. 6 shows a configuration of a MOS sensor according to the first conventional example described in Patent Reference 1 and Patent Reference 2. With reference to FIG. 6, the configuration of the MOS sensor according to the first conventional example including the column AD conversion circuits is described.
The MOS sensor according to the first conventional example includes, for each column of the pixels 1101, a column AD conversion circuit 1106 including a comparator 1107 and a column U/D counter 1208. The clock generating circuit 1120 supplies a clock signal 1121 to the column U/D counter 1208 in the column AD conversion circuit 1106, not just to a binary counter 1104. The binary value outputted from the binary counter 1104 is inputted to a DA conversion circuit 1105, and the DA conversion unit 1105 generates an analog ramp voltage (triangle wave) 1122 according to the input binary value. The analog ramp voltage 1122 is inputted to the comparator 1107 as a reference potential. Pixel signals are input from the pixel 1101 via a readout signal line 1103 to the other input of the comparator 1107. Furthermore, the digital value held in the column U/D counter in each column is outputted to outside the chip from an n-bit common output bus signal line 1126 and an output buffer 1109.
Next, the AD conversion in the MOS sensor according to the first conventional example is described.
First, the column U/D counter 1208 in the column AD conversion circuit 1106 is set to the down-counting mode for performing AD conversion of the reset level. The column U/D counter 1208 and the binary counter 1104 is initialized with the initialization signal (not shown), and the initial value of the analog ramp voltage 1122 is supplied to one of the input units of the comparator 1107. Next, the reset levels of pixels are read out from all of the pixels 1101 in the selected row, and supplied to the other input unit of the comparator 1107. With this, staring the input of the clock signal 1121 to the binary counter 1104 and the column U/D counter 1208 starts the binary counter 1104 counting from the initial value. Then, the DA conversion unit 1105 starts generating, from an initial value, the analog ramp voltage 1122 according to the count value of the binary counter 1104. Furthermore, the column U/D counter 1208 in the column AD conversion circuit 1106 starts down-counting the inputted clock signal 1121.
Next, when the magnitude relationship between two signals inputted to the comparator 1107 in a certain column is switched, that is, when the analog ramp voltage 1122 goes across the reset level at the comparator input in the certain column and the comparator 1107 is inverted, the clock signal 1121 inputted to the column counter 1208 in that column is masked, the column U/D counter 1208 stops down-counting, and holds the count value at the point in time. The count values of the analog ramp voltage 1122 and the column counter 1208 are synchronized with each other with the clock signal 1121, and thus the reset level of the pixel in that column is AD converted with the operation described above (However, note that the reset level is held as a minus value on the counter).
In order to assure that the AD conversion for the reset levels of all columns is performed, the clock signal 1121 is input to the binary counter 1104 from the clock generating circuit 1120 during a period corresponding to a predetermined AD conversion range of the reset level. The clock signal 1121 stops once when the AD conversion period of the reset level ends.
Next, in order to perform AD conversion at the signal level, the binary counter 1104 is set to the initial value again (the column U/D counter 1208 is not reset), the DA conversion unit 1105 to which the count value of the binary counter 1104 supplies the initial value of the analog ramp voltage 1122 to one of the input units of the comparator 1107. Afterwards, the column U/D counter 1208 is switched to the up-counting mode (Here, the column U/D counter 1208 needs hold a value obtained by down-counting).
Next, the signal levels of the pixels are read out from the pixel 1101 in the selected row, and supplied to the other input units of the comparator 1107. With this, resuming the input of the clock signal 1121 to the binary counter 1104 and the column U/D counter 1208 starts the binary counter 1104 counting from the initial value. Then, the DA conversion unit 1105 starts generating, from an initial value, the analog ramp voltage 1122 according to the count value of the binary counter 1104. The column U/D counter 1208 in the column AD conversion circuit 1106 starts up-counting the inputted clock signal 1121 with the value obtained by the down-counting as the initial value.
Next, when the magnitude relationship of the two signals inputted to the comparator 1107 in a certain column is switched that is, when the analog ramp voltage 1122 goes across the signal level at the comparator input in the certain column and the output signal from the comparator 1107 is inverted, the clock signal 1121 inputted to the column U/D counter 1208 in that column is masked, the column U/D counter 1208 stops up-counting, and holds the count value at the point in time. With the operations described above, AD conversion for the true signal level obtained by subtracting the reset level from the signal level of the pixels is performed.
In order to assure that AD conversion is performed on the signal level of all of the columns, the clock signal 1121 from the clock generating circuit 1120 is inputted to the binary counter 1104 during a period corresponding to a predetermined AD conversion range of the signal level.
With the process described above, processes from reading out signals from pixels in one row to the completion of AD conversion including CDS are performed.
As shown in the first conventional example, including a column U/D counter in each column of the AD conversion circuit facilitates the digital CDS. Here, it is necessary for the column U/D counter to be able to switch counting directions actively. Active switching of the counting direction refers to switching of operation mode from up-counting to down-counting (or from down-counting to up-counting), and resume the counting with the value held before the switching.
With regard to realization of digital CDS in the column AD conversion circuit in an image sensor, Patent Reference 3: Japanese Unexamined Patent Application Publication No. 2005-311933 discloses a technology particularly related to a column U/D counter, which is described as the second conventional example.
As disclosed in Patent Reference 3, a ripple counter which is an asynchronous counter is suitable for a column U/D counter in the column AD conversion circuit in terms of saving area, high speed, and low noise. However, a ripple carry counter which is a general asynchronous counter can be used in both counting directions by switching the connection for up-counting and the connection for down-counting with a switch, it is not suitable for active switching of the counting directions. FIG. 7 describes the reason why the ripple carry counter is not suitable with reference to FIG. 7.
FIG. 7 is a block diagram showing a configuration of a general asynchronous ripple carry counter shown in FIG. 18 of Patent Reference 3. In FIG. 7, selectors 922, 924, and 926 functions as switches to switch the counting directions. More specifically, the asynchronous counter up-counts when the control signal SW is in H (high level), and down-counts when the control signal SW is in L (low level). The clock input terminal CK in each FF (D flip-flop) which latches the data in the negative edge, one of the non-inverted output terminal Q or inverted output terminal NQ (indicated with a horizontal bar “-” over Q in the diagram) of the FF in the previous stage is input via a selector. Thus, depending on the value held in the FF of the previous stage, a negative edge appears on the selector output upon switching, and the input of the negative edge to the clock input terminal CK inverts the values held by some of the FFs, which leads to a broken count value.
As described above, when an asynchronous counter capable of switching the counting direction is configured with switches, even if independent operation (up-counting and down-counting) is realized by resetting immediately after the switching, it is not possible to resume the counting operation from the count value before the switching after up-down is switched. For example, the time chart in FIG. 19 of Patent Reference 3 shows broken count values when the counter in FIG. 7 (FIG. 18 in Patent Reference 3) is switched from down-counting to up-counting.
The technology disclosed in Patent Reference 3 in order to solve the problem is based on an idea that correct data is obtained by switching the bit with broken data (1 and 0 are switched) upon switching once again, regardless of the embodiments. FIG. 8 shows the circuit structure, and FIG. 9 shows the detailed drawing. FIGS. 10 and 11 show the waveforms during operation.
As shown in FIG. 8, a counter circuit 400 which is the conventional example has a structure that a plurality of negative-edge D flip-flops 412, 414, 416, and 418 (collectively 410) are connected by cascade connection. Each of the flip-flops 410 has an inverting output NQ (indicated with a horizontal bar over Q in the diagram) connected to a D input terminal thereof. Thus, the counter circuit 400 is capable of functioning as a 4-bit asynchronous counter.
Furthermore, between the respective adjacent pairs of the flip-flops 410, the counter circuit 400 includes three-input single-output tri-value switching units 422, 424, and 426 (collectively 420) that switch among three values, namely, the non-inverted output Q, the inverting output NQ, and a power supply (Vdd) level. More specifically, the tri-value switches 420 can be respectively configured by a pair of two-input single-output binary switching unites 432 and 433, a pair of two-input single-output binary switching unites 434 and 435, and a pair of two-input single-output binary switching unites 436 and 437, as shown in FIG. 9. These binary switching units are collectively referred to as binary switching unites 430.
In this example, each of the binary switching units 430 is switched according to switching control signals SL and FL generated at different timings as the two-bit switching control signals SW1 and SW2 supplied from a controller (not shown).
The binary switching units 432, 434, and 436 at the previous stages switch the non-inverted outputs Q and the inverting outputs NQ of the respectively associated flip-flops 410 according to the switching control signal SL, and pass the results to one of the input terminals of the associated binary switching unites 433, 435, and 437 at the subsequent stages. The binary switching unites 433, 435, and 437 at the subsequent stages switches between the data passed from the binary switching unites 432, 434, and 436 at the previous stages and the power supply level input to the other input terminals thereof according to the switching control signal FL, and input the results to the clock terminals CK of the subsequent flip-flops 410.
For example, the previous binary switching unit 430 (432, 434, and 436) selects the non-inverted output NQ and the inverting output Q of the preceding flip-flop 430 according to the switching control signal SL, and supplies it to one input terminal of the subsequent binary switching unit 430 (433, 435, and 437). The switching control signal SL controls the previous binary switching unit 430 (432, 434, and 436), thereby switching the counting operation of the counter circuit 400 between up-counting and down-counting.
The subsequent binary switch 430 (433, 435, and 437) selects one of the supply of the output (non-inverting output NQ or inverting output Q) of the preceding flip-flop 410, output from the previous binary switch 430 (432, 434, and 436) and H (high level signal) and outputs the selected signal to the clock terminal of the succeeding flip-flop 410.
The switching control signal FL controls the subsequent binary switch 430 (433, 435, and 437) so that the supply of the output of the preceding flip-flop 410 (non-inverting output NQ or inverting output Q) to the clock terminal CK of the succeeding flip-flop 410 is stopped for a predetermined period after switching of counting mode, and so that a signal corresponding to a clock is supplied to the clock terminal CK of the succeeding flip-flop 410 when the supply of non-inverting output NQ or inverting output Q is resumed. Thus, the count value before the switching is recovered when the counting mode is switched between the up-counting mode and the down-counting mode.
FIG. 10 is a timing chart for describing the operation of the counter circuit 400. In this example, the switching control signal SL is switched from high level to low level after up-counting is performed from a count value of 0 to a count value of 6 (t30). With this, the count value changes from “6” to “10”, and is broken.
Furthermore, after the switching of the switching control signal SL for switching counting mode, before a negative edge of the clock CK0 for down-counting is input to the first flip-flop 410, an active-H one-shot pulse is applied to the subsequent binary switches 433, 435, and 437 as the switching control signal FL (t32 to t34). With this, the broken count value “10” is fixed back to “6”.
The process of breaking and recovering of count value is described in more detail with reference to FIG. 11.
FIG. 11 illustrates clock signals CK1 to CK3 inputted to the clock input terminal of the flip-flops 414, 416, and 418. At the timing t30 in FIG. 11, the switching control signal SL changes from hi level to low level, the selectors 434 and 436 generate negative edges in the clock signal (A and B in FIG. 11). With this, the flip-flops 416 and 418 invert the values being held (C and D in FIG. 11). The count values are broken as described.
Furthermore, with a one-shot pulse in the switching control signal FL applied in the period between the timing t32 to timing t34, the selectors 435 and 437 generates negative edges in the clock signal CK2 and CK3 once more. With this, the flip-flops 416 and 418 invert the values being held again (E and F in FIG. 11). The count values are recovered as described.
With this, it is possible to substantially hold the count values before switching the counting mode, and down-counting can be performed after up-counting while maintaining the continuity of the count values.
As described above, with the second conventional example, active switching from up-counting to down-counting, or from down-counting to up-counting, is substantially possible since the broken data is recovered.